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24-bit capacitance-to-digital converter with temperature sensor preliminary technical data AD7747 rev. prc, 28. july 2006 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. features capacitance-to-digital converter new standard in single chip solutions interfaces to single or differential grounded sensors resolution down to 40 af (t hat is, up to 18.5-bit enob) accuracy: 8 ff linearity: 0.01% common-mode (not changing) capacitance up to 17 pf full scale (changing) capacitance range 8 pf update rate: 5 hz to 45 hz simultaneous 50 hz and 60 hz rejection at 8.1 hz update active shield for shielding sensor connection temperature sensor on-chip resolution: 0.1c, accuracy: 2c voltage input channel internal clock oscillator 2-wire serial interface (i 2 c ? -compatible) power 2.7 v to 5.25 v single-supply operation 1 ma current consumption operating temperature: C40c to +125c 16-lead tssop package applications automotive, industrial, and medical systems for pressure measurement position sensing proximity sensing level sensing flowmeters impurity detection general description the AD7747 is a high-resolution, ?? capacitance-to-digital converter (cdc). the capacitance to be measured is connected directly to the device inputs. the architecture features inherent high resolution (24-bit no missing codes, up to 18 bit effective resolution), high linearity (0.01%), and high accuracy (8 ff factory calibrated). the AD7747 capacitance input range is 8 pf (changing), while it can accept up to 17 pf common- mode capacitance (not changing), which can be balanced by a programmable on-chip digital-to-capacitance converter (capdac). the AD7747 is designed for single ended or differential capacitive sensors with one plate connected to ground. for floating (not grounded) capacitive sensors, the ad7745 or ad7746 are recommended. the part has an on-chip temperature sensor with a resolution of 0.1c and accuracy of 2c. the on-chip voltage reference and the on-chip clock generator eliminate the need for any external components in capacitive sensor applications. the part has a standard voltage input, which together with the differential reference input allows easy interface to an external temperature sensor, such as an rtd, thermistor, or diode. the AD7747 has a 2-wire, i 2 c-compatible serial interface. the part can operate with a single power supply 2.7 v to 5.25 v. it is specified over the automotive temperature range of C40c to +125c and are housed in a 16-lead tssop package. functional block diagrams scl sda clock generator temp sensor mux digital filter v dd i2c serial interface cap dac 1 excitation AD7747 c in1 (+) v in (+) v in ( - ) gnd 24-bit - ? modulator cap dac 2 shld c in1 ( - ) ref in (+) ref in ( - ) control logic calibration rdy voltage reference figure 1.
AD7747 preliminary technical data rev. prc | page 2 of 20 table of contents specifications..................................................................................... 3 timing specifications....................................................................... 5 absolute maximum ratings............................................................ 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 output noise and resolution specifications ................................ 9 serial interface ................................................................................ 10 read operation........................................................................... 10 write operation.......................................................................... 10 AD7747 reset ............................................................................. 11 general call................................................................................. 11 register descriptions ..................................................................... 12 status register ............................................................................. 13 cap data register....................................................................... 13 vt data register ........................................................................ 13 cap set-up register................................................................... 14 vt set-up register .................................................................... 14 exc set-up register.................................................................. 15 configuration register .............................................................. 16 cap dac a register .................................................................. 17 cap dac b register................................................................... 17 cap offset calibration register ............................................... 17 cap gain calibration register.................................................. 17 volt gain calibration register ................................................. 17 circuit description ........................................................................ 18 typical application diagram.................................................... 18 outline dimensions ....................................................................... 19 revision history march 2005revision prb: preliminary sampling, chip rev.s2 july 2006revision prc: preliminary sampling, chip rev.s3
preliminary technical data AD7747 rev. prc| page 3 of 20 specifications v dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v; gnd = 0 v; exc = v dd /2; C40c to +125c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments capacitive input conversion input range 8.192 pf 1 factory calibrated integral nonlinearity (inl) 2 0.01 % of fsr no missing codes 2 24 bit conversion time 124 ms resolution, p-p 16 bit conversion time 124 ms, see table 5 resolution effective 18.5 bit co nversion time 124 ms, see table 5 output noise, rms 15 af/ hz see table 5 absolute error 3 8 ff 1 25c, v dd = 5 v, after offset calibration offset error 2, 4 tbd af 1 after system offset calibration, excluding effect of noise 4 system offset calibration range 2 tbd pf offset drift vs. temperature tbd af/c gain error 5 tbd % of fs 25c, v dd = 5 v gain drift vs. temperature 2 C26 ppm of fs/c power supply rejection tbd ff/v normal mode rejection tbd db 50 hz 1%, conversion time 124 ms tbd db 60 hz 1%, conversion time 124 ms capdac full range 17 21 pf resolution 6 330 ff 6-bit capdac drift vs. temperature 2 26 ppm of fs/c excitation frequency 16 khz ac voltage across capacitance v dd /2 v configurable via digital interface average dc voltage across capacitance tbd mv active shielding allowed capacitance to gnd 2 50 pf shld pin temperature sensor 7 v ref internal resolution 0.1 c error 2 0.5 2 c internal temperature sensor 2 c external sensing diode 8 voltage input 7 v ref internal or v ref = 2.5 v differential vin voltage range v ref v absolute vin voltage 2 gnd ? 0.03 v dd + 0.03 v integral nonlinearity (inl) 3 15 ppm of fs no missing codes 2 24 bit conversion time = 122.1 ms resolution, p-p 16 bits conversion time = 62 ms see table 6 and table 7 output noise 3 v rms conversion time = 62 ms see table 6 and table 7 offset error 3 v offset drift vs. temperature 15 nv/c full-scale error 2, 9 0.025 0.1 % of fs full-scale drift vs. temperature 5 ppm of fs/c internal reference 0.5 ppm of fs/c external reference
AD7747 preliminary technical data rev. prc | page 4 of 20 parameter min typ max unit test conditions/comments average vin input current 300 na/v analog vin input current drift 50 pa/v/c power supply rejection 80 db internal reference, v in = v ref /2 power supply rejection 90 db external reference, v in = v ref /2 normal mode rejection 75 db 50 hz 1%, conversion time = 122.1 ms 50 db 60 hz 1%, conversion time = 122.1 ms common-mode rejection 95 db v in = 1 v internal voltage reference voltage 1.169 1.17 1.171 v t a = 25c drift vs. temperature 5 ppm/c external voltage reference input differential refin voltage 2 0.1 2.5 v dd v absolute refin voltage 2 gnd ? 0.03 v dd + 0.03 v average refin input current 400 na/v average refin input current drift 50 pa/v/c common-mode rejection 80 db serial interface logic inputs (scl, sda) v ih input high voltage 2.1 v v il input low voltage 0.8 v hysteresis 150 mv input leakage current (scl) 0.1 1 a open-drain output (sda) v ol output low voltage 0.4 v i sink = ? 6.0 ma i oh output high leakage current 0.1 1 a v out = v dd logic output ( rdy ) v ol output low voltage 0.4 v i sink = 1.6 ma, v dd = 5 v v oh output high voltage 4.0 v i source = 200 a, v dd = 5 v v ol output low voltage 0.4 v i sink = 100 a, v dd = 3 v v oh output high voltage v dd C 0.6 v i source = 100 a, v dd = 3 v power requirements v dd -to-gnd voltage 4.75 5.25 v v dd = 5 v, nominal 2.7 3.6 v v dd = 3.3 v, nominal i dd current 1 tbd ma digital inputs equal to v dd or gnd tbd ma v dd = 5 v tbd ma v dd = 3.3 v i dd current power-down mode tbd a digital inputs equal to v dd or gnd 1 capacitance units: 1 pf = 10 -12 f; 1 ff = 10 -15 f; 1 af = 10 -18 f. 2 specification is not production tested, but is supported by characterization data at initial product release. 3 factory calibrated. the absolute error includes factory gain calibration error, integral nonlin earity error, and offset error after system offset calibration, all at 25c. at different temperatures, compensation for g ain drift over temperature is required. 4 the capacitive input offset can be eliminated using a system offset calibration. the accuracy of the system offset calibration is limited by the offset calibration register lsb size (32 af) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. to m inimize the effect of the converter + system noise, longer conversion times should be used for system capacitive offset calibration. the system capacitance offset ca libration range is 1 pf, the larger offset can be removed using capdacs. 5 the gain error is factory calibrated at 25c. at different temperatures, compensation for gain drift over temperature is requi red. 6 the capdac resolution is six bits in the actual capdac full range. using the on-chip offset calibration or adjusting the capac itive offset calibration register can further reduce the cin offset or the unchanging cin component. 7 the vtchop bit in the vt setup register must be set to 1 for the specified temperature sensor and voltage input performance. 8 using an external temper ature sensing diode 2n3906, with nonideality factor n f = 1.008, connected as in figure tbd, with total serial resistance <100 ?. 9 full-scale error applies to both positive and negative full scale.
preliminary technical data AD7747 rev. prc| page 5 of 20 timing specifications v dd = 2.7 v to 3.6 v, or 4.75 v to 5.25 v; gnd = 0 v; input logic 0 = 0 v; input logic 1 = v dd ; C40c to +125c, unless otherwise noted. table 2. parameter min typ max unit test conditions/comments serial interface 1, 2 see figure 2 scl frequency 0 400 khz scl high pulse width, t high 0.6 s scl low pulse width, t low 1.3 s scl, sda rise time, t r 0.3 s scl, sda fall time, t f 0.3 s hold time (start condition), t hd;sta 0.6 s after this period, the first clock is generated set-up time (start condition), t su;sta 0.6 s relevant for repeated start condition data set-up time, t su;dat 0.1 s set-up time (stop condition), t su;sto 0.6 s data hold time, t hd;dat (master) 0 s bus-free time (between stop and start condition, t buf ) 1.3 s 1 sample tested during initial release to ensure compliance. 2 all input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. timing reference p oints at 50% for inputs and outputs. output load = 10 pf. p s t low t r t f t hd:sta t hd:dat t su:dat t su:sta t hd:sta t su:sto t high scl ps sd a t buf 05468-003 figure 2. serial interface timing diagram
AD7747 preliminary technical data rev. prc | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating positive supply voltage v dd to gnd ? 0.3 v to +6.5 v voltage on any input or output pin to gnd C0.3 v to v dd + 0.3 v esd rating (esd association human body model, s5.1) tbd v operating temperature range C40c to +125c storage temperature range C65c to +150c junction temperature 150c tssop package ja , (thermal impedance-to-air) 128c/w tssop package jc , (thermal impedance-to-case) 14c/w lead temperature, soldering vapor phase (60 sec) tbdc infrared (15 sec) tbdc stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without de tection. although th is product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data AD7747 rev. prc| page 7 of 20 pin configurations and function descriptions top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 AD7747 cin1(+) scl rdy shld tst cin1( - ) refin( - ) refin(+) nc sda nc vdd gnd nc vin(+) vin( - ) figure 3. AD7747 pin configuration (16-lead tssop) table 4. pin function descriptions pin no. mnemonic description 1 scl serial interface clock input. connects to the master cloc k line. requires pull-up resistor if not already provided in the system. 2 rdy logic output. a falling edge on this output indicates that a conversion on enabled channel(s) has been finished and the new data is available. alternati vely, the status register can be read via the 2-wire serial interface and the relevant bit(s) decoded to query the fi nished conversion. if not used, this pin should be left as an open circuit. 3 shld capacitive input active ac shielding. to eliminate the ci n parasitic capacitance to ground, the shld signal can be used to for shielding the connection be tween the sensor and cin. see the ma x allowed capacitance. if not used, this pin should be left as an open circuit. 4 tst this pin must be left as an open circuit for proper operation. 5, 6 refin(+), refin(C) differential voltage reference input for the voltage channel (adc). alternatively, the on-chip internal reference can be used for the voltage channel. these reference input pi ns are not used for conversion on capacitive channel(s) (cdc). if not used, these pins can be left as an open circuit or connected to gnd. 7 cin1(C) cdc negative capacitive input in differential mode. this pin is internally disconnected in single-ended cdc configuration. if not used, this pin sh ould be left as an open circuit. 8 cin1(+) cdc capacitive input (in single ended mode) or pos itive capacitive input (in differential mode). the measured capacitance is connected between one of the cin pins and gnd. if not used, this pin should be left as an open circuit. 9, 10 nc not connected. these pins shou ld be left as an open circuit. 11, 12 vin(+), vin(C) differential voltage input fo r the voltage channel (adc). these pins are also used to connect an external temperature sensing diode. if not used, these pins ca n be left as an open circuit or connected to gnd. 13 gnd ground pin. 14 vdd power supply voltage. this pin should be decoupled to gnd, using a low impedance capacitor, for example in combination with a 10 f tantalum and a 0.1 f multilayer ceramic. 15 nc not connected. this pin should be left as an open circuit. 16 sda serial interface bidirectional data. connects to the mast er data line. requires a pull-up resistor if not provided elsewhere in the system.
AD7747 preliminary technical data rev. prc | page 8 of 20 typical performance characteristics figure 4. figure 5. figure 6. figure 7. figure 8. figure 9.
preliminary technical data AD7747 rev. prc| page 9 of 20 output noise and resolu tion specifications the AD7747 resolution is limited by noise. the noise performance varies with the selected conversion time. table 5 shows typical noise performance and resolution for the capacitive channel. these numbers were generated from 1000 data samples acquired in continuous conversion mode, at an excitation of 16 khz, v dd /2, and with all cin and exc pins connected only to the evaluation board (no external capacitors.) table 6 and table 7 show typical noise performance and resolution for the voltage channel. these numbers were generated from 1000 data samples acquired in continuous conversion mode with vin pins shorted to ground. rms noise represents the standard deviation and p-p noise represents the difference between minimum and maximum results in the data. effective resolution is calculated from rms noise, and p-p resolution is calculated from p-p noise. table 5. typical capacitive input noise and resolution vs. conversion time conversion time (ms) output data rate (hz) C3db frequency (hz) rms noise (af/hz) rms noise (af) p-p noise (af) effective resolution (bits) p-p resolution (bits) 22.0 45.5 23.9 41.9 tbd tbd tbd tbd tbd tbd 40.0 25.0 76.0 13.2 124.0 8.1 6.9 15 40 250 18.5 16.0 154.0 6.5 184.0 5.4 219.3 4.6 table 6. typical voltage input nois e and resolution vs. conversion time, internal voltage reference conversion time (ms) output data rate (hz) C3db frequency (hz) rms noise (v) p-p noise (v) effective resolution (bits) p-p resolution (bits) 20.1 49.8 26.4 11.4 62 17.6 15.2 32.1 31.2 15.9 7.1 42 18.3 15.7 62.1 16.1 8.0 4.0 28 19.1 16.3 122.1 8.2 4.0 3.0 20 19.5 16.8 table 7. typical voltage input noise and resolution vs. conversion time , external 2.5 v voltage reference conversion time (ms) output data rate (hz) C3db frequency (hz) rms noise (v) p-p noise (v) effective resolution (bits) p-p resolution (bits) 20.1 49.8 26.4 14.9 95 18.3 15.6 32.1 31.2 15.9 6.3 42 19.6 16.8 62.1 16.1 8.0 3.3 22 20.5 17.7 122.1 8.2 4.0 2.1 15 21.1 18.3
AD7747 preliminary technical data rev. prc | page 10 of 20 serial interface the AD7747 supports an i 2 c-compatible 2-wire serial interface. the two wires on the i 2 c bus are called scl (clock) and sda (data). these two wires carry all addressing, control, and data information one bit at a time over the bus to all connected peripheral devices. the sda wire carries the data, while the scl wire synchronizes the sender and receiver during the data transfer. i 2 c devices are classified as either master or slave devices. a device that initiates a data transfer message is called a master, while a device that responds to this message is called a slave. to control the AD7747 device on the bus, the following protocol must be followed. first, the master initiates a data transfer by establishing a start condition, defined by a high-to- low transition on sda while scl remains high. this indicates that the start byte follows. this 8-bit start byte is made up of a 7-bit address plus an r/w bit indicator. all peripherals connected to the bus respond to the start condition and shift in the next 8 bits (7-bit address + r/w bit). the bits arrive msb first. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as the acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. an exception to this is the general call address, which is described later in this document. the idle condition is where the device monitors the sda and scl lines waiting for the start condition and the correct address byte. the r/w bit determines the direction of the data transfer. a logic 0 lsb in the start byte means that the master writes information to the addressed peripheral. in this case the AD7747 becomes a slave receiver. a logic 1 lsb in the start byte means that the master reads information from the addressed peri-pheral. in this case, the AD7747 becomes a slave transmitter. in all instances, the AD7747 acts as a standard slave device on the i 2 c bus. the start byte address for the AD7747 is 0x90 for a write and 0x91 for a read. read operation when a read is selected in the start byte, the register that is currently addressed by the address pointer is transmitted on to the sda line by the AD7747. this is then clocked out by the master device and the AD7747 awaits an acknowledge from the master. if an acknowledge is received from the master, the address auto- incrementer automatically increments the address pointer register and outputs the next addressed register content on to the sda line for transmission to the master. if no acknowledge is received, the AD7747 returns to the idle state and the address pointer is not incremented. the address pointers auto-incrementer allow block data to be written or read from the starting address and subsequent incremental addresses. in continuous conversion mode, the address pointers auto- incrementer should be used for reading a conversion result. that means, the three data bytes should be read using one multibyte read transaction rather than three separate single byte transactions. the single byte data read transaction may result in the data bytes from two different results being mixed. the same applies for six data bytes if both the capacitive and the voltage/temperature channel are enabled. the user can also access any unique register (address) on a one- to-one basis without having to update all the registers. the address pointer register contents cannot be read. if an incorrect address pointer location is accessed or, if the user allows the auto-incrementer to exceed the required register address, the following applies: ? in read mode, the AD7747 continues to output various internal register contents until the master device issues a no acknowledge, start, or stop condition. the address pointers auto-incrementers contents are reset to point to the status register at address 0x00 when a stop condition is received at the end of a read operation. this allows the status register to be read (polled) continually without having to constantly write to the address pointer. ? in write mode, the data for the invalid address is not loaded into the AD7747 registers but an acknowledge is issued by the AD7747. write operation when a write is selected, the byte following the start byte is always the register address pointer (subaddress) byte, which points to one of the internal registers on the AD7747. the address pointer byte is automatically loaded into the address pointer register and acknowledged by the AD7747. after the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master. a stop condition is defined by a low-to-high transition on sda while scl remains high. if a stop condition is ever encountered by the AD7747, it returns to its idle condition and the address pointer is reset to address 0x00. if a data byte is transmitted after the register address pointer byte, the AD7747 loads this byte into the register that is currently addressed by the address pointer register, send an acknowledge, and the address pointer auto-incrementer auto- matically increments the address pointer register to the next
preliminary technical data AD7747 rev. prc| page 11 of 20 internal register address. thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses. if a repeated start condition is encountered after the address pointer byte, all peripherals connected to the bus respond exactly as outlined above for a start condition, that is, a repeated start condition is treated the same as a start condition. when a master device issues a stop condition, it relinquishes control of the bus, allowing another master device to take control of the bus. hence, a master wanting to retain control of the bus issues successive start conditions known as repeated start conditions. AD7747 reset to reset the AD7747 without having to reset the entire i 2 c bus, an explicit reset command is provided. this uses a particular address pointer word as a command word to reset the part and upload all default settings. the AD7747 does not respond to the i 2 c bus commands (do not acknowledge) during the default values upload for approximately 150 s (max 200 s). the reset command address word is 0xbf. general call when a master issues a slave address consisting of seven 0s with the eighth bit (r/w bit) set to 0, this is known as the general call address. the general call address is for addressing every device connected to the i 2 c bus. the AD7747 acknowledges this address and read in the following data byte. if the second byte is 0x06, the AD7747 is reset, completely uploading all default values. the AD7747 does not respond to the i 2 c bus commands (do not acknowledge) during the default values upload for approximately 150 s (max 200 s). the AD7747 does not acknowledge any other general call commands. 1?7 8 9 1 ?7 8 9 1?7 8 9 p s start addr r/w ack subaddress ack data ack stop sdata sclock 05468-006 figure 10. bus data transfer data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data p s slave addr a(s) sub addr a(s) s slave addr a(s) data a(m) data p write sequence read sequence a(s) = no-acknowledge by slave a(m) = no-acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit a(s) a(m) 05468-007 figure 11. write and read sequences
AD7747 preliminary technical data rev. prc | page 12 of 20 register descriptions the master can write to or read from all of the AD7747 registers except the address pointer register, which is a write-only register. the address pointer register determines which register the next read or write operation accesses. all communications with the part through the bus start with an access to the address pointer register. after the part has been accessed over the bus and a read/write operation is selected, the address pointer register is set up. the address pointer register determines from or to which register the operation takes place. a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. table 8. register summary address pointer bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register (dec) (hex) dir default value - - - - - rdy rdyvt rdycap status 0 0x00 r 0 0 0 0 0 1 1 1 cap data h 1 0x01 r capacitive channel datahigh byte, 0x00 cap data m 2 0x02 r capacitive channel datamiddle byte, 0x00 cap data l 3 0x03 r capacitive channel datalow byte, 0x00 vt data h 4 0x04 r voltage/temper ature channel datahigh byte, 0x00 vt data m 5 0x05 r voltage/tempera ture channel datamiddle byte, 0x00 vt data l 6 0x06 r voltage/temper ature channel datalow byte, 0x00 capen - capdiff - - - - - cap setup 7 0x07 r/w 0 0 0 0 0 0 0 0 vten vtmd1 vtmd0 extref - - vtshort vtchop vt setup 8 0x08 r/w 0 0 0 0 0 0 0 0 - - - - excdac excen exclvl1 exclvl0 exc setup 9 0x09 r/w 0 0 0 0 0 0 1 1 vtfs1 vtfs0 capfs2 capfs1 capfs0 md2 md1 md0 configuration 10 0x0a r/w 1 0 1 0 0 0 0 0 dacaena - daca6-bit value cap dac a 11 0x0b r/w 0 0 0x00 dacbenb - dacb6-bit value cap dac b 12 0x0c r/w 0 0 0x00 cap offset h 13 0x0d r/w capacitive offset calibrationhigh byte, 0x80 cap offset l 14 0x0e r/w capacitive offset calibrationlow byte, 0x00 cap gain h 15 0x0f r/w capacitive gain ca librationhigh byte, factory calibrated cap gain l 16 0x10 r/w capacitive gain ca librationlow byte, factory calibrated volt gain h 17 0x11 r/w voltage gain cali brationhigh byte, factory calibrated volt gain l 18 0x12 r/w voltage gain ca librationlow byte, factory calibrated
preliminary technical data AD7747 rev. prc| page 13 of 20 status register address pointer 0x00, read only, default value 0x07 this register indicates the status of the converter. the status register can be read via the 2-wire serial interface to query a finished conversion. the rdy pin reflects the status of the rdy bit. therefore, the rdy pin high-to-low transition can be used as an alternative indication of the finished conversion. table 9. status register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic - - - - - rdy rdyvt rdycap default 0 0 0 0 0 1 1 1 table 10. bit mnemonic description 7-3 - not used, always read 0. 2 rdy rdy = 0 indicates that conversion on the enabled channel(s) has been finished and new unread data is available. if both capacitive and voltage/temperature channels are en abled, the rdy bit is chan ged to 0 after conversion on both channels is finished. the rdy bi t returns to 1 either when data is read or prior to finishing the next conversion. if, for example, only the capacitive channel is enab led, then the rdy bit reflects the rdycap bit. 1 rdyvt rdyvt = 0 indicates that a conversion on the volt age/temperature channel has been finished and new unread data is available. 0 rdycap rdycap = 0 indicates that a conversion on the capa citive channel has been finished and new unread data is available. cap data register 24 bits, address pointer 0x01, 0x02, 0x03, read-only, default value 0x000000 capacitive channel output data. the register is updated after finished conversion on the capacitive channel, with one exception: when the serial interface read operation from the cap data register is in progress, the data register is not updated and the new capacitance conversion result is lost. the stop condition on the serial interface is considered to be the end of the read operation. therefore, to prevent data corruption, all three bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface. to prevent losing some of the results, the cap data register should be read before the next conversion on the capacitive channel is finished. the 0x000000 code represents negative full scale (C8.192 pf), the 0x800000 code represents zero scale (0 pf), and the 0xffffff code represents positive full scale (+8.192 pf). vt data register 24 bits, address pointer 0x04, 0x05, 0x06, read-only, default value 0x000000 voltage/temperature channel output data. the register is updated after finished conversion on the voltage channel or temperature channel, with one exception: when the serial interface read operation from the vt data register is in progress, the data register is not updated and the new voltage/temperature conversion result is lost. the stop condition on the serial interface is considered to be the end of the read operation. therefore, to prevent data corruption, all three bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface. for voltage input, code 0 represents negative full scale (Cv ref ), the 0x800000 code represents zero scale (0 v), and the 0xffffff code represents positive full scale (+v ref ). to prevent losing some of the results, the vt data register should be read before the next conversion on the voltage/ temperature channel is finished. for the temperature sensor, the temperature can be calculated from code using the following equation: te mperature (c) = ( code /2048) ? 4096
AD7747 preliminary technical data rev. prc | page 14 of 20 cap set-up register address pointer 0x07, default value 0x00 capacitive channel setup. table 11. cap set-up register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic capen - capdiff - - - - - default 0 0 0 0 0 0 0 0 table 12. bit mnemonic description 7 capen capen = 1 enables capacitive channel for single conversion, continuous con version, or calibration. 6 - this bit must be 0 for proper operation. 5 capdiff diff = 1 sets differential mode on the selected capacitive input. 4-0 - these bits must be 0 for proper operation. vt set-up register address pointer 0x08, default value 0x00 voltage/temperature channel setup. table 13. vt set-up register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic vten vtmd1 vtmd0 extref - - vtshort vtchop default 0 0 0 0 0 0 0 0 table 14. bit mnemonic description 7 vten vten = 1 enables voltage/temperature channel for si ngle conversion, continuous conversion, or calibration. voltage/temperature channe l input configuration. vtmd1 vtmd0 channel input 0 0 internal temperature sensor 0 1 external temperature sensor diode 1 0 v dd monitor 6 5 vtmd1 vtmd0 1 1 external voltage input (vin) 4 extref extref = 1 selects an external reference voltage co nnected to refin(+), refin(C) for the voltage input or the v dd monitor. extref = 0 selects the on-chip internal reference. the internal reference must be used with the internal temperature sensor for proper operation. 3-2 - these bits must be 0 for proper operation. 1 vtshort vtshort = 1 internally shorts the voltage/temperature ch annel input for test purposes. 0 vtchop = 1 vtchop = 1 sets internal cho pping on the voltage/temperature channel. the vtchop bit must be set to 1 for the spec ified voltage/temperature channel performance.
preliminary technical data AD7747 rev. prc| page 15 of 20 exc set-up register address pointer 0x09, default value 0x03 capacitive channel excitation setup. table 15. exc set-up bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic - - - - excdac excen exclvl1 exclvl0 default 0 0 0 0 0 0 1 1 table 16. bit mnemonic description 7-4 - these bits must be 0 for proper operation. 3 excdac capdac excitation. this bit must be se t to 1 for the proper capacitive channel operation 2 excen cin and ac shld excitation. this bit must be set to 1 for the proper capacitive channel operation excitation voltage level. exclvl1 exclvl0 voltage on cap exc pin low level exc pin high level 0 0 v dd /8 v dd 3/8 v dd 5/8 0 1 v dd /4 v dd 1/4 v dd 3/4 1 0 v dd 3/8 v dd 1/8 v dd 7/8 1 0 exclvl1, exclvl0 1 1 v dd /2 0 v dd
AD7747 preliminary technical data rev. prc | page 16 of 20 configuration register address pointer 0x0a, default value 0xa0 converter update rate and mode of operation setup. table 17. configuration register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic vtf1 vtf0 capf2 capf1 capf0 md2 md1 md0 default 0 0 0 0 0 0 0 0 table 18. bit mnemonic description voltage/temperature channel digital filter setupconversion time/update rate setup. vtchop = 1 vtf1 vtf0 conversion time (ms) update rate (hz) C3 db frequency (hz) 0 0 20.1 49.8 26.4 0 1 32.1 31.2 15.9 1 0 62.1 16.1 8.0 7 6 vtf1 vtf0 1 1 122.1 8.2 4.0 capacitive channel digital filter setup conversion time/update rate setup. cap chop = 0 capf2 capf1 capf0 conversion time (ms) update rate C3 db frequency (hz) 0 0 0 22.0 45.5 0 0 1 23.9 41.9 0 1 0 40.0 25.0 0 1 1 76.0 13.2 1 0 0 124.0 8.1 1 0 1 154.0 6.5 1 1 0 184.0 5.5 5 4 3 capf2 capf1 capf0 1 1 1 219.3 4.6 converter mode of operation setup. md2 md1 md0 mode 0 0 0 idle 0 0 1 continuous conversion 0 1 0 single conversion 0 1 1 power-down 1 0 0 - 1 0 1 capacitance system offset calibration 1 1 0 capacitance or voltage system gain calibration 2 1 0 md2 md1 md0 1 1 1
preliminary technical data AD7747 rev. prc| page 17 of 20 cap dac a register address pointer 0x0b, default value 0x00 capacitive dac setup. table 19. cap dac a register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic dacaena - daca6-bit value default 0 0 0x00 table 20. bit mnemonic description 7 dacaena dacaena = 1 connects capacitive da ca to the positive capacitance input. 6 - this bit must be 0 for proper operation. 5-1 daca daca value, code 0x00 0 pf, code 0x3f full range. cap dac b register address pointer 0x0c, default value 0x00 capacitive dac setup. table 21. cap dac b register bit map bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic dacaenb - dacb6-bit value default 0 0 0x00 table 22. bit mnemonic description 7 dacbenb dacbenb = 1 connects capacitive da cb to the negative capacitance input. 6 - this bit must be 0 for proper operation. 5-1 dacb dacb value, code 0x00 0 pf, code 0x3f full range. cap offset calibration register 16 bits, address pointer 0x0d, 0x0e, default value 0x8000 the capacitive offset calibration register holds the capacitive channel zero-scale calibration coefficient. the coefficient is used to digitally remove the capacitive channel offset. the register value is updated automatically following the execution of a capacitance offset calibration. the capacitive offset calibra- tion resolution (cap offset register lsb) is less than tbd af; the full range is tbd pf. cap gain calibration register 16 bits, address pointer 0x0f, 0x10, default value 0xxxxx capacitive gain calibration register. the register holds the capacitive channel full-scale factory calibration coefficient. volt gain calibration register 16 bits, address pointer 0x11,0x12, default value 0xxxxx voltage gain calibration register. the register holds the voltage channel full-scale factory calibration coefficient.
AD7747 preliminary technical data rev. prc | page 18 of 20 circuit description active ac shield concept the AD7747 measures capacitance between cin and ground. that means any capacitance to ground on signal path between AD7747 cin pin(s) and sensor is included in the AD7747 conversion result. the parasitic capacitance of the sensor connections can easily be in the same, if not even higher order than the capacitance of the sensor itself. if that parasitic capacitance is stable, it can be treated as a non-changing capacitive offset. however, the parasitic capacitance of sensor connections is often changing as result of mechanical movement, changing ambient temperature, ambient humidity, etc. these changes would be seen as drift in the conversion result and may significantly compromise the system accuracy. to eliminate the cin parasitic capacitance to ground, the AD7747 shld signal can be used for shielding the connection between the sensor and cin. the shld output is basically the same signal waveform as the excitation of the cin pin, the shld is driven to the same voltage potential as the cin pin. therefore, there is no ac current between cin and shld pins and any capacitance between these pins doesn't get involved in the cin charge transfer. ideally, the cin to shld capacitance doesn't have any contribution to the AD7747 result. to get the best result, locate the AD7747 as close as possible to the capacitive sensor. keep the connection between the sensor and AD7747 cin pin and also the return path between sensor ground and the AD7747 gnd pin short. shield the pcb track to cin pin and connect the shielding to the AD7747 shld pin. also, if a shielded cable is used for sensor connection, the shield should be connected to the AD7747 shld pin. typical application diagram host system 0.1uf 10uf + +3v / +5v power supply scl sda v dd gnd rdy clock generator temp sensor mux digital filter i2c serial interface cap dac 1 excitation AD7747 v in (+) v in ( - ) 24-bit - ? modulator cap dac 2 ref in (+) ref in ( - ) control logic calibration voltage reference c in1 (+) shld c in1 ( - ) figure 12. basic application diagram for a differential capacitive sensor
preliminary technical data AD7747 rev. prc | page 19 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 13. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters
AD7747 preliminary technical data rev. prc | page 20 of 20 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners.

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